My Resume

RESUME

VIPIN KUMAR TYAGI

OBJECTIVE:: Looking for a challenging job where I can contribute my academic qualifications and personal skills towards the success of the organization along with my professional career; a job that will earn me satisfaction and enable me to learn more and more in life – a continuous learning process.

Pursuing M.Tech.Signal Processing N.S.I.TNew Delhi

Contact No.:09891835810

Correspondence Address
H.No. 20, Village Tajpur (Near Gurdwara)
Badarpur,New Delhi – 110 044
Tel. No. 011 – 29892111

E-Mail:
vipinktyagi@gmail.com
itsvip007@yahoo.co.in

Personal Data
Father’s Name :Mr. R. S. Tyagi
Mother’s Name:Mrs Urmila Tyagi
Date of Birth :24th Dec. 1983
Sex :Male
Nationality :Indian
Marital Status : Single
Languages : English, Hindi

EDUCATION
Professional Qualification:

2007 M.Tech. (Signal Processing) - 71%(First Year).
Institute: NSIT, DELHI Delhi University, Delhi

2005 B.Tech. (Electronics & Instrumentation) - 74.82%.
College : Hindustan College of Science & Technology, Mathura (Affiliated to U.P. Tech. University, Lucknow)

Academic Qualifications:

1999 10+2 from S.S.K.Inter College, Hapur (Ghaziabad) (U.P. Board) 64%.
1997 10 from S.S.K. Inter College, Hapur (Ghaziabad) (U.P. Board) 67%

AREA OF INTEREST
VLSI: MOS Circuits & MOS physics, Design of Analog Circuits. Design and Synthesis of Digital Circuits using Verilog HDL.
SIGNAL PROCESSING: Digital Signal Processing, Image Processing, Speech Processing
EMBEDDED SYSTEM: Microprocessors & Application of AVR microcontroller


COMPUTER PROFICIENCY
Tools : MATLAB
Languages : C, Assembly (AVR Microcontroller),8051,8086.
Operating System : LINUX, Windows XX
HDL : VERILOG HDL

INDUSTRIAL EXPOSURE
1.Worked as “Project Trainee” at nSys Design System Ltd, Delhi from June 12th, 06 to August 11st, 06 . PROJECT: Design of SATA in Verilog HDL.
MY ROLE: Develop the architecture of Data link layer & then provide complete functionality. (Using Verilog HDL)
Platform: UNIX (Red Hat)

2. Working as Project trainee in Atrenta India Pvt Ltd.,Noida from 14th March,07.


SUMMER TRAININGS
1. Project Title : Universal axle Counter
Duration : June 10th 2004-july 9th 2004

2. Project Title : Solar Photovoltaic Cells
Duration : July 1st 2003-july 31st 2003

Organization : Central Electronics Limited, Sahibabad (Ghaziabad)


STRENGHTS
Ø Ability to live and work in a group excellently.
Ø Strong learner and innovative.
Ø Ability to lead and motivate colleagues.
Ø Ability to deliver even in exigent conditions.

ACHIEVEMENTS/EXTRA CO-CURRICULAR
Ø Branch Topper in B. Tech.
Ø 4th rank in M.Tech.
Ø GATE 2005 Score 96.47 Percentile (EC)
Ø GATE 2004 Score 90.79Percentile (EC)
Ø Campus placement in WIPRO-VLSI group.
Ø Works as R&D Coordinator (Electronics Dept.) in College for 1 years.
Ø Paper presented on Solar Energy in National Level Competition.
Ø Participate in Electronics Model Show in National Level Competition
Ø Participation in sports and curricular activities
Ø Organized XVI annual games in NSIT, Delhi.
Ø HOBBIES: Playing Cricket and solving Sudoku

PROJECTS
1. M.Tech. Thesis- Quantum Computation Using MATLAB

In this thesis work I have implemented four Quantum Algorithms in MATLAB (Shor’s Factorization algorithm, Deutsch Algorithm, Deutsch-Jozsa Algorithm and Grover’s search Algorithm) and also finds the application of Grover’s search algorithm in Image Processing.

2. B.Tech. Final Year Project-SMS Remote Controller
Responsibilities Handled: -
1. Development of Logic & Algorithm
2. Development of Programming

3. Project Title- Distance Measurement Using Sonar (AVR Microcontroller Based)

4. Project Title- Automatic Traffic Light Controller (VHDL based)

5. Project Title- Automatic Temperature Controlled Fan (using IC LM355)

REFERENCES
1. Mr. V.K. Sharma 2. Dr. Harish Parthasarathy
Dean HR & III Professor and Associate Head
H.C.S.T. Mathura, U.P. NSIT, Delhi
Mobile No. 09897501810 Ph. No. 011-25099112



(Vipin Kumar Tyagi)